/*
 * Copyright (C) 2015 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 */


#ifndef _ANLG_PHY_G10_REG_H
#define _ANLG_PHY_G10_REG_H

#define CTL_BASE_ANLG_PHY_G10 SPRD_ANLG_PHY_G10


#define REG_ANLG_PHY_G10_ANALOG_BIA_THM_0_PHY_BIA_THM_OPT        ( CTL_BASE_ANLG_PHY_G10 + 0x0000 )
#define REG_ANLG_PHY_G10_ANALOG_BIA_THM_0_PHY_BIA_THM_CTRL0      ( CTL_BASE_ANLG_PHY_G10 + 0x0004 )
#define REG_ANLG_PHY_G10_ANALOG_BIA_THM_0_REG_SEL_CFG_0          ( CTL_BASE_ANLG_PHY_G10 + 0x0008 )

/*---------------------------------------------------------------------------
// Register Name   : REG_ANLG_PHY_G10_ANALOG_BIA_THM_0_PHY_BIA_THM_OPT
// Register Offset : 0x0000
// Description     : 
---------------------------------------------------------------------------*/

#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ICALGAMMA(x)                             (((x) & 0x1F) << 24)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ICALDATOFFSET(x)                         (((x) & 0x7FF) << 13)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ICALDATSLOPE(x)                          (((x) & 0x1FFF))

/*---------------------------------------------------------------------------
// Register Name   : REG_ANLG_PHY_G10_ANALOG_BIA_THM_0_PHY_BIA_THM_CTRL0
// Register Offset : 0x0004
// Description     : 
---------------------------------------------------------------------------*/

#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ICALCONFIGSEL(x)                         (((x) & 0x3) << 5)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_OTSTEMPERATURETRIP                       BIT(4)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ITSEN                                    BIT(3)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ITSPOWERGOOD                             BIT(2)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_IANACHOPCTR                              BIT(1)
#define BIT_ANLG_PHY_G10_ANALOG_BIA_THM_0_ITSRST                                   BIT(0)

/*---------------------------------------------------------------------------
// Register Name   : REG_ANLG_PHY_G10_ANALOG_BIA_THM_0_REG_SEL_CFG_0
// Register Offset : 0x0008
// Description     : 
---------------------------------------------------------------------------*/

#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ICALGAMMA                        BIT(7)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ICALDATOFFSET                    BIT(6)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ICALDATSLOPE                     BIT(5)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ICALCONFIGSEL                    BIT(4)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ITSEN                            BIT(3)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ITSPOWERGOOD                     BIT(2)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_IANACHOPCTR                      BIT(1)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_BIA_THM_0_ITSRST                           BIT(0)


#endif // _ANLG_PHY_G10_REG_H
